2026-10-11T20:21:21Z https://api.figshare.com/v2/oai

oai:figshare.com:article/34044512 2026-10-01T11:19:40Z category_146 category_19 category_45 category_734 category_931 portal_87 item_type_3 month_year_10_2026

Modeling of an Efficient FPGA-based Convolution Accelerator Using Triangle Walk Sand Cat Swarm Optimisation Peer Mohamed M (25156274) Deepa P (25156277) Space Science Pharmacology Sociology Biological Sciences not elsewhere classified Information Systems not elsewhere classified Accelerator convolution FPGA triangle walk sand cat swarm optimization <p>FPGA-based accelerators for convolution operations often face significant challenges in achieving optimal resource utilisation while maintaining high performance. Conventional designs tend to consume excessive resources, leading to a compromise in both accuracy and execution speed. In this work, we introduce a novel approach using Triangle Walk Sand Cat Swarm Optimisation (TWSCO) to optimise Look-Up Tables (LUTs) and carry chains for more efficient FPGA implementations. The proposed method integrates Booth Multipliers Radix 4 (BM-R4) with a Multiply-Accumulator (MAC) architecture that explicitly accumulates partial products, enabling simultaneous multiplication and addition without interference. We perform extensive simulations using Xilinx Vivado 2021.2, where we evaluate key performance indicators, such as LUT and carry chain reduction, power consumption, and processing delay. The results demonstrate that our TWSCO-based design outperforms existing solutions, achieving substantial reductions in resource usage and improvements in both power efficiency and computational speed, making it an ideal candidate for high-performance, resource-efficient convolution acceleration on FPGAs.</p> <p><b>Highlights</b></p> <p>Robust resource-efficient multipliers are proposed.</p> <p>Triangle walk Sand Cat Swarm Optimisation (TWSCO)-based LUTs and carry chains are employed.</p> <p>Booth Multipliers-Radix 4 (BM-R4) is modelled without the interruption of addition and multiplication outcomes.</p> <p>Simulations are conducted in Xilinx Vivado 2021.2 synthesis.</p> <p>LUT reduction, carry chain reduction, power, and delay are analysed.</p> 2026-10-01T11:19:40Z Dataset Dataset 10.6084/m9.figshare.34044512.v1 https://figshare.com/articles/dataset/Modeling_of_an_Efficient_FPGA-based_Convolution_Accelerator_Using_Triangle_Walk_Sand_Cat_Swarm_Optimisation/34044512 CC BY 4.0